diff --git a/arch/arm/cpu/arm920t/at91rm9200/lxt972.c b/arch/arm/cpu/arm920t/at91rm9200/lxt972.c
index 260d393..f02cfdd 100644
--- a/arch/arm/cpu/arm920t/at91rm9200/lxt972.c
+++ b/arch/arm/cpu/arm920t/at91rm9200/lxt972.c
@@ -52,8 +52,8 @@
 	unsigned short Id1, Id2;
 
 	at91rm9200_EmacEnableMDIO (p_mac);
-	at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR1, &Id1);
-	at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR2, &Id2);
+	at91rm9200_EmacReadPhy(p_mac, MII_PHYSID1, &Id1);
+	at91rm9200_EmacReadPhy(p_mac, MII_PHYSID2, &Id2);
 	at91rm9200_EmacDisableMDIO (p_mac);
 
 	if ((Id1 == (0x0013)) && ((Id2  & 0xFFF0) == 0x78E0))
@@ -170,18 +170,18 @@
 	unsigned short value;
 
 	/* Set lxt972 control register */
-	if (!at91rm9200_EmacReadPhy (p_mac, PHY_BMCR, &value))
+	if (!at91rm9200_EmacReadPhy (p_mac, MII_BMCR, &value))
 		return FALSE;
 
 	/* Restart Auto_negotiation  */
-	value |= PHY_BMCR_RST_NEG;
-	if (!at91rm9200_EmacWritePhy (p_mac, PHY_BMCR, &value))
+	value |= BMCR_ANRESTART;
+	if (!at91rm9200_EmacWritePhy (p_mac, MII_BMCR, &value))
 		return FALSE;
 
 	/*check AutoNegotiate complete */
 	udelay (10000);
-	at91rm9200_EmacReadPhy(p_mac, PHY_BMSR, &value);
-	if (!(value & PHY_BMSR_AUTN_COMP))
+	at91rm9200_EmacReadPhy(p_mac, MII_BMSR, &value);
+	if (!(value & BMSR_ANEGCOMPLETE))
 		return FALSE;
 
 	return (lxt972_GetLinkSpeed (p_mac));
diff --git a/arch/arm/cpu/arm926ejs/davinci/lxt972.c b/arch/arm/cpu/arm926ejs/davinci/lxt972.c
index ce3e41c..733d413 100644
--- a/arch/arm/cpu/arm926ejs/davinci/lxt972.c
+++ b/arch/arm/cpu/arm926ejs/davinci/lxt972.c
@@ -39,9 +39,9 @@
 {
 	u_int16_t id1, id2;
 
-	if (!davinci_eth_phy_read(phy_addr, PHY_PHYIDR1, &id1))
+	if (!davinci_eth_phy_read(phy_addr, MII_PHYSID1, &id1))
 		return(0);
-	if (!davinci_eth_phy_read(phy_addr, PHY_PHYIDR2, &id2))
+	if (!davinci_eth_phy_read(phy_addr, MII_PHYSID2, &id2))
 		return(0);
 
 	if ((id1 == (0x0013)) && ((id2  & 0xfff0) == 0x78e0))
@@ -105,19 +105,19 @@
 {
 	u_int16_t tmp;
 
-	if (!davinci_eth_phy_read(phy_addr, PHY_BMCR, &tmp))
+	if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
 		return(0);
 
 	/* Restart Auto_negotiation  */
-	tmp |= PHY_BMCR_RST_NEG;
-	davinci_eth_phy_write(phy_addr, PHY_BMCR, tmp);
+	tmp |= BMCR_ANRESTART;
+	davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
 
 	/*check AutoNegotiate complete */
 	udelay (10000);
-	if (!davinci_eth_phy_read(phy_addr, PHY_BMSR, &tmp))
+	if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
 		return(0);
 
-	if (!(tmp & PHY_BMSR_AUTN_COMP))
+	if (!(tmp & BMSR_ANEGCOMPLETE))
 		return(0);
 
 	return (lxt972_get_link_speed(phy_addr));
diff --git a/arch/arm/cpu/ixp/npe/miiphy.c b/arch/arm/cpu/ixp/npe/miiphy.c
index 4b0201a..a04779a 100644
--- a/arch/arm/cpu/ixp/npe/miiphy.c
+++ b/arch/arm/cpu/ixp/npe/miiphy.c
@@ -85,16 +85,16 @@
 	unsigned short ctl, adv;
 
 	/* Setup standard advertise */
-	miiphy_read (devname, addr, PHY_ANAR, &adv);
-	adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
-		PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
-		PHY_ANLPAR_10);
-	miiphy_write (devname, addr, PHY_ANAR, adv);
+	miiphy_read (devname, addr, MII_ADVERTISE, &adv);
+	adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 |
+		LPA_100FULL | LPA_100HALF | LPA_10FULL |
+		LPA_10HALF);
+	miiphy_write (devname, addr, MII_ADVERTISE, adv);
 
 	/* Start/Restart aneg */
-	miiphy_read (devname, addr, PHY_BMCR, &ctl);
-	ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
-	miiphy_write (devname, addr, PHY_BMCR, ctl);
+	miiphy_read (devname, addr, MII_BMCR, &ctl);
+	ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
+	miiphy_write (devname, addr, MII_BMCR, ctl);
 
 	return 0;
 }
diff --git a/arch/arm/cpu/ixp/npe/npe.c b/arch/arm/cpu/ixp/npe/npe.c
index 2e68689..857bcad 100644
--- a/arch/arm/cpu/ixp/npe/npe.c
+++ b/arch/arm/cpu/ixp/npe/npe.c
@@ -359,15 +359,15 @@
 
 	debug("%s: 1\n", __FUNCTION__);
 
-	miiphy_read (dev->name, p_npe->phy_no, PHY_BMSR, &reg_short);
+	miiphy_read (dev->name, p_npe->phy_no, MII_BMSR, &reg_short);
 
 	/*
 	 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
 	 */
-	if ((reg_short & PHY_BMSR_AUTN_ABLE) && !(reg_short & PHY_BMSR_AUTN_COMP)) {
+	if ((reg_short & BMSR_ANEGCAPABLE) && !(reg_short & BMSR_ANEGCOMPLETE)) {
 		puts ("Waiting for PHY auto negotiation to complete");
 		i = 0;
-		while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
+		while (!(reg_short & BMSR_ANEGCOMPLETE)) {
 			/*
 			 * Timeout reached ?
 			 */
@@ -378,7 +378,7 @@
 
 			if ((i++ % 1000) == 0) {
 				putc ('.');
-				miiphy_read (dev->name, p_npe->phy_no, PHY_BMSR, &reg_short);
+				miiphy_read (dev->name, p_npe->phy_no, MII_BMSR, &reg_short);
 			}
 			udelay (1000);	/* 1 ms */
 		}
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index d4abeb1..a2d2bd6 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -888,14 +888,14 @@
 			udelay(10000);	/* wait 10ms */
 		}
 		for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
-			phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+			phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2));
 #ifdef ET_DEBUG
 			printf("PHY type 0x%x pass %d type ", phytype, pass);
 #endif
 			if (phytype != 0xffff) {
 				phyaddr = phyno;
 				phytype |= mii_send(mk_mii_read(phyno,
-								PHY_PHYIDR1)) << 16;
+								MII_PHYSID1)) << 16;
 
 #ifdef ET_DEBUG
 				printf("PHY @ 0x%x pass %d type ",phyno,pass);
diff --git a/arch/powerpc/cpu/ppc4xx/miiphy.c b/arch/powerpc/cpu/ppc4xx/miiphy.c
index 3b28122..206c476 100644
--- a/arch/powerpc/cpu/ppc4xx/miiphy.c
+++ b/arch/powerpc/cpu/ppc4xx/miiphy.c
@@ -89,60 +89,60 @@
 	u16 exsr = 0x0000;
 #endif
 
-	miiphy_read (devname, addr, PHY_BMSR, &bmsr);
+	miiphy_read (devname, addr, MII_BMSR, &bmsr);
 
 #if defined(CONFIG_PHY_GIGE)
-	if (bmsr & PHY_BMSR_EXT_STAT)
-		miiphy_read (devname, addr, PHY_EXSR, &exsr);
+	if (bmsr & BMSR_ESTATEN)
+		miiphy_read (devname, addr, MII_ESTATUS, &exsr);
 
-	if (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH)) {
+	if (exsr & (ESTATUS_1000XF | ESTATUS_1000XH)) {
 		/* 1000BASE-X */
 		u16 anar = 0x0000;
 
-		if (exsr & PHY_EXSR_1000XF)
-			anar |= PHY_X_ANLPAR_FD;
+		if (exsr & ESTATUS_1000XF)
+			anar |= ADVERTISE_1000XFULL);
 
-		if (exsr & PHY_EXSR_1000XH)
-			anar |= PHY_X_ANLPAR_HD;
+		if (exsr & ESTATUS_1000XH)
+			anar |= ADVERTISE_1000XHALF;
 
-		miiphy_write (devname, addr, PHY_ANAR, anar);
+		miiphy_write (devname, addr, MII_ADVERTISE, anar);
 	} else
 #endif
 	{
 		u16 anar, btcr;
 
-		miiphy_read (devname, addr, PHY_ANAR, &anar);
-		anar &= ~(0x5000 | PHY_ANLPAR_T4 | PHY_ANLPAR_TXFD |
-			  PHY_ANLPAR_TX | PHY_ANLPAR_10FD | PHY_ANLPAR_10);
+		miiphy_read (devname, addr, MII_ADVERTISE, &anar);
+		anar &= ~(0x5000 | LPA_100BASE4 | LPA_100FULL |
+			  LPA_100HALF | LPA_10FULL | LPA_10HALF);
 
-		miiphy_read (devname, addr, PHY_1000BTCR, &btcr);
+		miiphy_read (devname, addr, MII_CTRL1000, &btcr);
 		btcr &= ~(0x00FF | PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD);
 
-		if (bmsr & PHY_BMSR_100T4)
-			anar |= PHY_ANLPAR_T4;
+		if (bmsr & BMSR_100BASE4)
+			anar |= LPA_100BASE4;
 
-		if (bmsr & PHY_BMSR_100TXF)
-			anar |= PHY_ANLPAR_TXFD;
+		if (bmsr & BMSR_100FULL)
+			anar |= LPA_100FULL;
 
-		if (bmsr & PHY_BMSR_100TXH)
-			anar |= PHY_ANLPAR_TX;
+		if (bmsr & BMSR_100HALF)
+			anar |= LPA_100HALF;
 
-		if (bmsr & PHY_BMSR_10TF)
-			anar |= PHY_ANLPAR_10FD;
+		if (bmsr & BMSR_10FULL)
+			anar |= LPA_10FULL;
 
-		if (bmsr & PHY_BMSR_10TH)
-			anar |= PHY_ANLPAR_10;
+		if (bmsr & BMSR_10HALF)
+			anar |= LPA_10HALF;
 
-		miiphy_write (devname, addr, PHY_ANAR, anar);
+		miiphy_write (devname, addr, MII_ADVERTISE, anar);
 
 #if defined(CONFIG_PHY_GIGE)
-		if (exsr & PHY_EXSR_1000TF)
+		if (exsr & ESTATUS_1000_TFULL)
 			btcr |= PHY_1000BTCR_1000FD;
 
-		if (exsr & PHY_EXSR_1000TH)
+		if (exsr & ESTATUS_1000_THALF)
 			btcr |= PHY_1000BTCR_1000HD;
 
-		miiphy_write (devname, addr, PHY_1000BTCR, btcr);
+		miiphy_write (devname, addr, MII_CTRL1000, btcr);
 #endif
 	}
 
@@ -152,21 +152,21 @@
 	 */
 	u16 adv;
 
-	miiphy_read (devname, addr, PHY_ANAR, &adv);
-	adv |= (PHY_ANLPAR_ACK  | PHY_ANLPAR_TXFD | PHY_ANLPAR_TX |
-		PHY_ANLPAR_10FD | PHY_ANLPAR_10);
-	miiphy_write (devname, addr, PHY_ANAR, adv);
+	miiphy_read (devname, addr, MII_ADVERTISE, &adv);
+	adv |= (LPA_LPACK  | LPA_100FULL | LPA_100HALF |
+		LPA_10FULL | LPA_10HALF);
+	miiphy_write (devname, addr, MII_ADVERTISE, adv);
 
-	miiphy_read (devname, addr, PHY_1000BTCR, &adv);
+	miiphy_read (devname, addr, MII_CTRL1000, &adv);
 	adv |= (0x0300);
-	miiphy_write (devname, addr, PHY_1000BTCR, adv);
+	miiphy_write (devname, addr, MII_CTRL1000, adv);
 
 #endif /* defined(CONFIG_PHY_DYNAMIC_ANEG) */
 
 	/* Start/Restart aneg */
-	miiphy_read (devname, addr, PHY_BMCR, &bmcr);
-	bmcr |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
-	miiphy_write (devname, addr, PHY_BMCR, bmcr);
+	miiphy_read (devname, addr, MII_BMCR, &bmcr);
+	bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
+	miiphy_write (devname, addr, MII_BMCR, bmcr);
 
 	return 0;
 }